摘要
Clock skew是数字集成电路设计中一个重要的因素。本文比较了在同步电路设计中 0 clock skew和非 0clock skew时钟分布对电路性能的影响 ,分析了通过调整时钟树中 CL OCK SKEW来改善电路性能的方法 ,从而说明非 0 clock skew时钟分布是如何提高同步电路运行的最大时钟频率的。
Clock skew is a very important factor in digital IC design fields. Comparison of impact to the performance of synchronization circuits made by zero and non zero clock skew scheduling is given, and methods of improving the performance of circuits through modulating clock skew are analyzed to show how non zero clock skew scheduling can improve the performance of circuits.
出处
《电子器件》
CAS
2002年第4期431-434,共4页
Chinese Journal of Electron Devices
