摘要
本文介绍了一种提升芯片FPGA原型验证时序性能的方法。通过提出一种创新的时钟设计方法,解决了传统方法的时序收敛瓶颈,提高了芯片FPGA原型验证系统时序收敛性能,使每次从芯片RTL移植到FPGA时都能够时序稳定收敛。
This paper introduces a design method for improving the timing performance of chip FPGA prototype verification system.By proposing an innovation clock design method,the timing convergence bottleneck of traditional methods has been solved,and the timing convergence performance of the chip FPGA prototype verification system has been improved,enabling stable timing convergence every time the chip RTL is ported to FPGA.
作者
刘刚
王延斌
王西国
LIU Gang;WANG Yan-bin;WANG Xi-guo(CEC Huada Electronic Design Co.,Ltd,Beijing Key Laboratory of RFID Chip Test Technology)
出处
《中国集成电路》
2026年第3期40-44,共5页
China lntegrated Circuit
