摘要
随着集成电路工艺越来越先进,布局规划对芯片时序收敛的影响日益显著。传统布局方法依赖设计者经验,难以应对多宏单元复杂设计,导致时序收敛效率低下。近年来,自动化布局技术逐渐成熟,显著提升了时序性能与布线质量。本研究基于传统布局、自由形式摆放(FFP)、混合FFP、机器学习以及约束机器学习这五种布局方式,在时序层面的表现展开系统综述。重点对比分析五种布局方式在22nm工艺节点下的拥塞状况,以及在多模多角(MMMC)条件下对比分析时序违例情况。研究结果表明,相较于其他四种布局方式,约束机器学习布局通过融合智能预测与物理设计约束,在时序收敛方面表现最优,为高性能低功耗芯片设计提供了有效支撑。
With the advancement of integrated circuit manufacturing processes,layout planning has become increasingly critical for achieving optimal chip timing convergence.Traditional layout methods,which rely heavily on designer experience,often struggle with complex multi-macrocell designs,resulting in inefficient timing convergence.Recent years have seen significant progress in automated layout technologies,which have substantially improved both timing performance and routing quality.This study systematically evaluates five layout approaches-traditional layout,freeform placement(FFP),hybrid FFP,machine learning,and constrained machine learning-based on their timing-level performance.The analysis focuses on congestion patterns at the 22nm process node and timing violations under multi-mode multi-angle(MMMC)conditions.Results demonstrate that constrained machine learning layouts,by integrating intelligent prediction with physical design constraints,outperform the other four methods in timing convergence,providing robust support for high-performance,low-power chip design.
作者
蒋家宇
江富荣
JIANG Jia-yu;JIANG Furong(Information and Communication School,Guilin University of Electronic Technology;Guangxi Key Laboratory of Precision Navigation Technology and Application,Guilin University of Electronic Technology)
出处
《中国集成电路》
2026年第3期60-65,共6页
China lntegrated Circuit
基金
广西科技计划项目(桂科AB23026120,桂科AA24263029,桂科AA24263010)
国家自然科学基金(U23A20280,62471153,U25A20397)
南宁市科学研究与技术开发计划(20231029,20231011)
广西产研计划项目(CYY-HT2023-JSJJ-0023-1、CYY-HT2023-JSJJ-0024-1)
广西自治区重大人才项目资助
北斗位置服务及边海防安全应用广西高校工程研究中心资助。
