摘要
在航天计量测试领域,高速数据采集设备需要对多种数据进行采集和存储,具有瞬间接收且数据量大的特点。目前国内多数高性能计测仪器的核心控制芯片均基于国外芯片设计,存在“卡脖子”问题。因此,利用国产FPGA(现场可编程门阵列)芯片和DDR3(第三代双倍数据速率)存储芯片,采用多级FIFO(First Input First Output)流水线设计和双DDR3存储“乒乓”读写方式,通过MIG(Memory Interface Generator)接口实现对DDR3芯片的读写操作控制,经测试验证,在缓冲速率高达4 Gb/s时,数据也无丢帧或紊乱现象,实现了高速大容量数据缓存。
In the field of space metrology and testing,high-speed data acquisition equipment needs to collect and store multiple types of data,which has the characteristic of receiving large amounts of data in a short period of time.At present,the core control chips of most high-performance measurement and testing instruments in China are based on foreign chip designs,which poses the“chokepoint”problem.using domestic FPGA chips and DDR3 memory chips,employing a multi-level FIFO pipeline and a dual DDR3 memory ping-pong read-write method,through the MIG interface,the read and write operation of DDR3 chip is realized.The test verifies that the designed data volume is 4 Gb/s,and there is no frame loss and data disturbance.The high-speed and large-capacity data cache has been realized.
作者
关越
李炳臻
贺智国
逯宏超
蒋维
崔广智
GUAN Yue;LI Bingzhen;HE Zhiguo;LU Hongchao;JIANG Wei;CUI Guangzhi(Beijing Institute of Structure and Environment Engineering,Beijing 100076,China)
出处
《宇航计测技术》
2025年第6期95-99,共5页
Journal of Astronautic Metrology and Measurement
