摘要
坐标旋转数字计算机(CORDIC)因其简易的硬件实现,在电子测量、雷达探测和图像处理等诸多领域得到了广泛应用。高基数和并行CORDIC能够有效降低CORDIC迭代延迟,能够满足实时性要求较高的需求。但是,两者均引入了可变缩放因子,这增加了缩放因子的计算复杂度,引起额外的资源消耗。相比而言,免缩放CORDIC算法消除了可变的缩放因子。然而,现有的大多数免缩放CORDIC算法虽然能保持一定精度并支持较大收敛范围,但是在资源消耗和延迟指标上仍有待提升。因此,提出了一种结合查找表(LUT)和并行免缩放迭代的混合CORDIC算法及其计算结构设计,采用具有更少非零项的近似角度确定查找表与并行免缩放迭代角度边界的方法,扩展了并行免缩放迭代所支持的角度收敛范围;提出将并行迭代分为二并行迭代和四并行迭代来平衡每级迭代的计算复杂度,以保证整体设计性能的方法,LUT用于将位于区间(-π/2,π/2)的大角度输入快速折叠至二并行迭代所支持的角度收敛范围;然后执行二并行免缩放迭代,使得剩余角度进入到四并行免缩放迭代所支持的角度收敛范围;最后执行四并行免缩放迭代并输出CORDIC迭代结果。所提出的设计使用Verilog硬件描述语言实现,并在现场可编程门阵列(FPGA)上完成验证和性能评估。实验结果表明,与已有相关研究相比,本文提出的设计在保持相同精度和收敛范围的同时,资源消耗降低23.1%,延迟降低22.1%。
The coordinate rotation digital computer(CORDIC)algorithm has the feature of simple hardware implementation.It has been widely applied in various fields,such as electronic measurement,radar detection,and image processing.High-radix and parallel CORDIC effectively reduce CORDIC iteration latency to meet the real-time requirements.However,both approaches introduce a variable scaling factor,increasing the computational complexity and results in additional resource consumption.In comparison,scaling-free(SF)CORDIC algorithm eliminates the variable scaling factor.However,the most existing SF-CORDIC algorithms still require improvements in resource consumption and latency performance,while maintaining acceptable accuracy and supporting a wide convergence range.Therefore,this article proposes a hybrid CORDIC algorithm and its computing architecture design,which combines the look-up table(LUT)and parallel SF iterations.A method is proposed to determine the angle boundary between the LUT and parallel SF iterations using approximate angles with fewer non-zero terms,which extends the convergence range supported by the parallel SF iterations;furthermore,a method is proposed to divide the parallel SF iterations into two-parallel and four-parallel SF iterations to balance the computational complexity of each iteration stage,ensuring the overall design performance.Specifically,the LUT is used to rapidly fold a large-angle input located in the range(-π/2,π/2)into the convergence range supported by the two-parallel SF iterations.Then,the two-parallel SF iterations are performed to bring the residual angle into the convergence range supported by the four-parallel SF iterations.Finally,the four-parallel SF iterations are performed and the CORDIC iteration results are output.The proposed design is implemented in Verilog hardware description language and validated on field-programmable gate array(FPGA).Experimental results demonstrate that,compared with the existing designs,the proposed design reduces resource consumption by 23.1% and latency by 22.1%,while maintaining comparable accuracy and convergence range.
作者
魏学静
孙皓
彭宇
刘连胜
Wei Xuejing;Sun Hao;Peng Yu;Liu Liansheng(School of Electronics and Information Engineering,Harbin Institute of Technology,Harbin 150080,China)
出处
《电子测量与仪器学报》
北大核心
2025年第6期174-183,共10页
Journal of Electronic Measurement and Instrumentation
关键词
免缩放CORDIC
FPGA
低延迟
低资源消耗
并行迭代
scaling-free CORDIC
field-programmable gate array
low latency
low resource consumption
parallel iterations
