摘要
提出了一种双路径锁相环(DP-PLL)结合Hershey-Kiss波形作为调制信号的展频时钟发生器(SSCG)。基于和差调制器(DSM)实现的SSCG中,锁相环的带宽需要在调制线性度和量化噪声抑制之间进行折中,较低的环路带宽引入了较大的环路滤波器电容,使得难以实现片上集成。采用双路径锁相环实现的电容倍增技术节省芯片面积,同时,Hershey-Kiss波形作为调制信号获得更高的EMI降低效果。基于SMIC 180 nm CMOS工艺下完成电路设计,仿真结果表明,展频时钟发生器工作在750 MHz情况下,实现了0.25%~0.5%的展频深度可调节,展频深度开启0.5%的情况下,峰值能量降低最高可达17.52 dB。芯片整体面积为0.51 mm×0.48 mm,整体功耗为23.5 mW。
A spread-spectrum clock generator(SSCG)based on dual-path phase-locked loop(DP-PLL)combined with Hershey-Kiss waveform as the modulation profile is proposed.The SSCG based on delta-sigma modulator(DSM)in which the bandwidth of phase-locked loop requires a trade-off between modulation linearity and quantization noise rejection,the lower loop bandwidth introduces larger loop filter capacitance,making it difficult to be integrated on-chip.The capacitance multiplication technique achieved using a dual-path phase-locked loop saves chip area,meanwhile,the Hershey-Kiss waveform is used as the modulation signal to obtain higher EMI reduction.Implemented in SMIC 180 nm CMOS technology,simulation results show that the spread spectrum clock generator operates at 750 MHz,realizing an adjustable spread ratio from 0.25%to 0.5%,a 17.52 dB reduction in the peak power spectrum with 0.5%spread ratio.The die area of the SSCG is 0.51 mm×0.48 mm,with an overall power consumption is 23.5 mW.
作者
朱武
耿锦霞
孟煦
ZHU Wu;GENG Jinxia;MENG Xu(Institute of VLSI Design,Hefei University of Technology.,Hefei 230601,P.R.China;IC Design Web-Cooperation Research Center of MOE,Hefei 230601,P.R.China)
出处
《微电子学》
北大核心
2025年第2期213-221,共9页
Microelectronics
基金
国家重点研究与发展计划(2023YFB4403804)。
