摘要
随着10 kV及以上超高压碳化硅(SiC)功率器件在柔性输电等领域的需求增长,开发低位错、低缺陷密度、长少子寿命的厚外延材料成为关键挑战,是当前SiC材料研究的核心问题。基于单片水平式SiC外延设备,通过引入双界面调制缓冲层外延生长技术,成功实现了对缓冲层与衬底及漂移层之间界面应力的调控,显著降低了外延片基平面位错密度,结合漂移层生长速率、缓冲层工艺以及C/Si比的协同优化,显著提升了4H-SiC厚外延材料的性能。实验结果表明:优化后的缓冲层工艺通过渐变掺杂设计有效调控界面应力,将基平面位错密度从1.5 cm^(-2)降至0.07 cm^(-2);同时,通过将生长速率提升至70μm/h并优化C/Si比至0.85,成功制备了厚度100μm、掺杂浓度2.5×10^(14)cm^(-3)的高质量外延层,原生少子寿命均值达1.76μs,材料均匀性及表面缺陷密度均满足10 kV以上超高压器件耐压区需求。
With the increasing demands for 10 kV and higher ultra-high voltage silicon carbide(SiC)power devices in fields such as flexible power transmission,the development of thick epitaxial materials with low dislocation,low defect density and long minority carrier lifetime has become a critical challenge,representing a core issue in current SiC material research.Based on single-wafer horizontal SiC epitaxial equipment,interface stress regulation between buffer layers and substrate/drift layers was successfully achieved through implementation of dual-interface modulated buffer layer epitaxial growth technology,which significantly reduces basal plane dislocation density in epitaxial wafers.Through synergistic optimization of drift layer growth rate,buffer layer processes,and C/Si ratio,the performance of 4H-SiC thick epitaxial materials is remarkably enhanced.Experimental results demonstrate that the optimized buffer layer process effectively modulates interface stress through graded doping design,reducing basal plane dislocation density from 1.5 cm^(-2)to 0.07 cm^(-2).Simultaneously,by increasing growth rate to 70μm/h and optimizing C/Si ratio to 0.85,high-quality epitaxial layers with 100μm thickness and doping concentration of 2.5×10^(14)cm^(-3)was successfully fabricated.The average native minority carrier lifetime reaches 1.76μs,with material uniformity and surface defect density meeting the requirements for voltage-resistant regions in 10 kV and higher ultra-high voltage devices.
作者
房玉龙
李帅
芦伟立
王健
李建涛
王波
Fang Yulong;Li Shuai;Lu Weili;Wang Jian;Li Jiantao;Wang Bo(The 13^(th)Research Institute,CETC,Shijiazhuang 050051,China)
出处
《微纳电子技术》
2025年第6期20-26,共7页
Micronanoelectronic Technology
关键词
超高压
基平面位错
C/Si比
双界面调制缓冲层
少子寿命
ultra-high voltage
basal plane dislocation
C/Si ratio
dual-interface modulated buffer layer
minority carrier lifetime
