摘要
进入3 nm以下技术节点后,堆叠纳米片环栅晶体管(stacked-nanosheets GAA transistors)因为拥有更为出色的沟道控制能力和输出更大的驱动电流,将替代鳍型晶体管(FinFET)成为全新一代的CMOS技术架构;但同时在沟道形成、内侧墙、寄生沟道、源漏寄生电阻/电容、以及沟道应力设计等关键技术领域面临挑战。本文就上述关键技术进行了较为全面的阐述,并结合这些技术的开发阐述了设计-工艺协同优化(DTCO)在先进CMOS工艺开发中的重要作用。
For 3 nm technology and beyond,due to the capability of better controlling the channel and outputting larger drive-current,stacked-nanosheets gate-all-around(GAA)transistors will replace FinFETs to be the new generation of CMOS technology.Meanwhile,key challenges will be confronted regarding channel formation,inner-spacer,parasitic channel,parasitic S/D resistance/capacitance,and channel strain engineering.All these aspects are comprehensively discussed,and the pivot role of DTCO in the advanced CMOS technology development has been illustrated and demonstrated.
作者
徐敏
张卫
陈鲲
杨静雯
刘桃
吴春蕾
王晨
XU Min;ZHANG Wei;CHEN Kun;YANG Jingwen;LIU Tao;WU Chunlei;WANG Chen(School of Microelectronics,Fudan University,Shanghai 200433,China;Shanghai Integrated Circuit Manufacturing Innovation Center Co.,Ltd.,Shanghai 200072)
出处
《微纳电子与智能制造》
2021年第1期27-31,共5页
Micro/nano Electronics and Intelligent Manufacturing
