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半精度浮点数处理器的设计与验证 被引量:1

Design and verification of the half-precision floating point processor
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摘要 半精度浮点数处理器HFPP(Half-Precision Floating Point Processor)是一种16位浮点数处理器。HFPP基于Verilog HDL实现了加减、乘、除、开方等运算,采用了BOOTH算法与华莱士树加法器,以及改进的开平方算法。验证方面采用了基于UVM(Universal Verification Methodology)的验证平台。最终结论表明,算法相比普通移位算法速度提高了50%~70%。覆盖率提高了50%。 The HFPP( Half-Precision Floating Point Processor) is a 16-bit processor. HFPP based on Verilog HDL,has functions of addition and subtraction,multiplication,division,square root etc.,using the BOOTH algorithm and Wallace tree adder,and improved square root algorithm. Compared to the general algorithm,it increased by 50% to 70% in speed. The verification part is constructed on a UVM( Universal Verification Methodology) based platform with a 50% increase in coverage.
出处 《信息技术》 2018年第1期136-140,共5页 Information Technology
关键词 浮点数 半精度 图像 高效算法 UVM验证方法学 floating point number half-precision image efficient algorithm UVM
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