摘要
在甚低频(VLF)通信技术中,对甚低频接收机的研究具有重要意义。论文提出一种基于FPGA的甚低频接收机,给出该系统的设计、实现和验证过程。主要实现10k Hz^50k Hz信号的滤波、增益调整、采样和数字下变频(DDC)等处理功能。处理后数据通过以太网接口传输到计算机进行信号的解调和分析工作。通过指令可以设置甚低频接收采集处理模块的工作模式为DDC模式或者直接采样滤波输出模式。该接收机能以低廉的成本获取准确的标准授时信号,具有扩展性好、带宽大、可靠性强、便于携带等优点,为甚低频信号的检测提供了一种可行的技术方案。
In VLF communication technology, the research of VLF receiver is of great significance. A VLF receiver based on FPGA is proposed in this paper. The design, implementation and verification of the system are given. 10kHz-50kHz signal filtering, gain adjustment, sampling and DDC processing functions are mainly achieved. The data is transmitted to the computer through the Ethernet interface for signal demodulation and analysis. The working mode of the VLF receiving and collecting processing module can be set up by the instruction, and the output mode of the DDC mode or the direct sampling filter is provided. The receiver can cheaply obtain the standard time signal accurately, with good scalability, high bandwidth, high reliability, carrying easyly, etc. It provides a feasible technical scheme for the detection of VLF signal.
作者
张驰
芮国胜
王瑞
薛鹏
ZHANG Chi RUI Guosheng WANG Rui XUE Peng(Graduate Students＇ Brigade, Naval Aeronautical and Astronautical University, Yantai 264001 Electronic Information Engineering Department, Naval Aeronautical and Astronautical University, Yantai 264001)
出处
《计算机与数字工程》
2017年第9期1866-1869,1887,共5页
Computer & Digital Engineering
基金
国家自然科学基金项目(编号:41606117
41476089
61671016)资助
