摘要
介绍了一种基于FPGA的便携式低频时码接收机系统的设计方案。该接收机的特点是体积小,功耗低,方便户外工作人员携带。描述了该接收机的硬件系统结构,给出了软件算法。硬件结构中,使用了ALTERA公司的EP2C70F672C8芯片,软件部分在QuartusⅡ开发环境下完成。系统测试结果表明,按本方案设计的接收机集成度高,可靠性好,易扩展,易升级,具有一定的实用价值。
A design of portable low frequency time-code receiver based on FPGA（field programmable gate array） is introduced.The receiver is characterized by small volume and low power consumption,and it is very convenient to carry it outdoors.The design of hardware structure and software algorithm is described in this paper.The chip of EP2C70F672C8 produced by the ALTERA company is adopted in the hardware structure,and the software design is completed in Quartus Ⅱ environment.The experimental results indicate that this receiver has merits such as high integrity level,good reliability,and being easy to be expanded and upgraded.Thus this receiver is of certain practical value.
出处
《时间频率学报》
CSCD
2012年第2期88-95,共8页
Journal of Time and Frequency
