摘要
针对译码器对于多种码率的支持不够灵活和译码器存储资源较多而导致实现复杂度较大、面积及功耗较大的问题,提出了一种低存储量兼容多码率的QC-LDPC码分层译码器结构。它采用一种新的译码算法和存储器压缩技术减少存储器的使用,采用备份存储器的方法,仅用很少的存储器代价,解决了LDPC码存在的存储器读写冲突。与传统部分并行译码器相比,改进的译码器存储资源相对于传统译码器节约了20%,采用硬件资源复用,译码器能够兼容三种码率。用modelsim对编码器和译码器的功能进行验证,并在altera公司Stratix IV系列的EP4SGX530芯片上综合测试。结果表明,当译码器工作频率为204 MHz、迭代次数为10的情况下,译码器吞吐量可达321.4 Mb/s。
For that the decoder is not flexible enough in support of code rates and more storage resources of the decoder would cause fairly high complexity of realization, large area and power consumption, a hierarchical decoder structure of QC-LDPC code with low memory compatible with multi-rate is proposed. The new algorithm and memory compression technology is adopted to reduce the use of memory resources and split-memory architecture to solve the memory read-and-write conflict problem. Compared with the traditional partial parallel decoder, the modified decoder has a storage-resource saving 20%. With hardware-resource sharing, the decoder could support three code rates. Experiment on encoder and decoder system with modelsim and the comprehensive test on EP4SGX530 chip indicate that the throughput capacity of the decoder could reach 321.4 Mb/s when the decoder is at working frequency of 204 MHz and iterations number of 10.
出处
《通信技术》
2017年第8期1614-1619,共6页
Communications Technology
基金
国家自然科学基金项目(No.61302095
No.61401165)
福建省自科学基金计划资助项目(No.2014J05076
No.2014J01243
No.2015J01262)~~
关键词
LDPC
低存储量
并行分层
多码率
LDPC
low memory requirement
parallellayered
multi-rate
