摘要
介绍了一种自主研发的全集成315 MHz/433 MHz射频发射芯片中编码器的设计.利用分频器产生二选一数据选择器的选通信号,通过逐级筛选,将并行地址数据转变为串行数据.采用Verilog HDL语言进行设计,使用Modelsim进行仿真验证,基于和舰0.18μm CMOS工艺布局布线.样片测试结果表明,编码器基础时钟频率为250kHz时可以很好地满足设计指标和功能要求.
The encoder of a kind of self-developed fully-integrated 315 MHz RF launching chip is de- signed. Frequency divider is used to generate strobe signals for either-or data selectors. Through step-by- step selection, the parallel address data are turned into serial data. Verilog HDL language is used for de- sign,Modelsim for simulation,and HeJian 0.18μm CMOS as process technology. The results show that the encoder satisfies the designing requirements when the basic clock frequency is 250 kHz.
出处
《吉首大学学报（自然科学版）》
CAS
2017年第1期24-27,共4页
Journal of Jishou University(Natural Sciences Edition)
基金
国家自然科学基金资助项目(61563017)
