摘要
针对SRAM型FPGA,提出了一种基于动态可重构技术的容错设计方法,根据瞬态错误概率的高低来动态控制系统的冗余程度。在错误率低的时候,系统采用双备份比较(DWC),具有较低的面积开销和功耗;在错误率高的时候,系统切换到三模冗余(TMR)排除单个错误的影响。采用基于代理逻辑(Proxy LUT)和早期获取部分可重构(EAPR)的设计方法,以ISCAS’85benchmark电路中的大型代表电路为验证模块,叙述了动态可重构的容错结构的实现过程,并重点验证了动态可重构容错设计方法和其它静态容错方法相比,在面积和功耗上的优势,结果表明动态可重构容错结构相比混合容错结构而言,其面积开销和功率消耗较小。
This paper proposes a fault‐tolerant design method for SRAM‐based FPGA by using dynamic reconfiguration technology .This method adjusts the degree of redundancy of the system depending on the various soft error rate .When the error rate is low ,the system adopts duplication with compare （DWC） which has lower area overhead and power consumption .If the soft error rate is high ,the system switches to the triple modular redundancy （TMR） to eliminate the effects of a single error .By taking the representative circuits in ISCAS ’85 benchmark as redundant modules ,this paper explains the implementation of fault‐tolerant structure of dynamic reconfiguration by using Proxy LUT and EAPR （early‐access partial reconfiguration ） technology .Finally ,the paper compares the simulation results with the state‐of‐the‐art static fault tolerant technique and thus validates the advantages of the proposed method in the aspects of area and power consumption ,its area overhead and power consumption is small .
出处
《电子测量技术》
2016年第11期41-45,共5页
Electronic Measurement Technology
基金
国家自然科学基金(61401205)资助项目
关键词
容错
动态部分重构
面积开销
功耗
fault-tolerant
partial dynamic reconfiguration
area overhead
power consumption
