摘要
该文采用最新的基于EAPR的动态部分重构的方法,利用IP核构建片上系统的思想,设计出PowerPC405加FPGA的硬件平台设计可重构系统,FPGA采用CompactFlash配置方式,由硬核处理器PPC405控制内部配置访问接口实现动态部分可重构。该设计实现了硬件资源的时分复用,提高了FPGA的利用率,缩短了重配置时间,并在VirtexⅡPro FPGA上进行了功能验证。
In this paper,we adopt the latest design methodology of dynamic partial reconfiguration of FPGA based on EAPR which is proposed by Xilinx and use IP core to build system on chip.This paper also provides a way of design a dynamically reconfigurable system based on PPC405 and FPGA hardware platform to configure and reconfigure FPGA selected a CompactFlash configuration mode.The PowerPC405,the hardware core microprocessor in XC2VP30,is used to manage the ICAP to implement the dynamic partial reconfiguration pr...
出处
《杭州电子科技大学学报（自然科学版）》
2011年第1期37-40,共4页
Journal of Hangzhou Dianzi University：Natural Sciences
基金
国家自然科学基金资助项目(60773042)
