摘要
航天用FPGA设计复杂度越来越高,其表现之一就是设计中存在多个时钟域,当信号从一个时钟域进入另一个时钟域,即不同时钟域之间发生数据交互时,就会带来信号跨时钟域产生的亚稳态问题(CDC问题)。亚稳态问题虽普遍存在,但依靠传统的验证手段即功能仿真或者时序仿真是很难定位的,提出一种分层次、多模式的跨时钟域验证方法,为跨时钟域问题分析确认提供强有力的参考。
The FPGA design used in aerospace is becoming more and more complex, which includes the appearance of multi clock domain in design. The issue with metastability will arise when a signal traverses from one clock domain into another. Although the metastability exists widely, it is difficult to locate the issue based on traditional verification methods, including function simulation and timing simulation. This essay will propose a hierarchical and multi-mode verification method for clock domain crossing, which provides a strong reference for analyzing clock domain crossing issue.
作者
王菲
张莎莎
王茜
Wang Fei Zhang Shasha Wang Xi(771 Institute of China Aerospace,Xi＇an 710119, China)
出处
《电子技术应用》
北大核心
2017年第1期43-45,49,共4页
Application of Electronic Technique
关键词
FPGA
跨时钟域
亚稳态
验证方法
FPGA
clock domain crossing
metastable
verification method
