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布图规划约束对VLSI设计性能的影响 被引量：2

The Influence on VLSI Design Performance by Constraints in Floorplanning
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摘要 布图规划处于芯片物理设计的前端,对VLSI整体性能起着至关重要的作用.给出了平面布图规划约束的介绍,通过在布图规划阶段进行约束嵌入的实验,考查了约束对VLSI布图规划设计性能的影响.在IBM-HB+Benchmark Suites上嵌入约束的实验表明,约束设置会给VLSI布图规划带来一定的影响,甚至会改善设计质量. The flcorplanning plays a vital role to the final VLSI performance because it is in the earlier stage of the physical design In this paper, we introduce several kinds of constraints in floorplanning. We investigate the influence caused by constraint in floorplanning The experimental results on IBM-HB＋ Benchmark Suites show that the constraint embedding had some influence on the floorplanning design, sometimes it may improve the quality of the design
作者 聂廷远 李坤龙 高久顼
机构地区 青岛理工大学
出处 《微电子学与计算机》 CSCD 北大核心 2016年第11期104-108,共5页 Microelectronics & Computer
基金 国家自然科学基金项目(61572269)
关键词 VLSI 平面布图规划 物理设计 约束 VLSI floorplanning physical design constraint
分类号 TP302.1 [自动化与计算机技术—计算机系统结构]
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参考文献12

  • 1郝冬艳,张明,郑伟.低功耗VLSI芯片的设计方法[J].微电子学与计算机,2007,24(6):137-139. 被引量：15
  • 2Yan J Z, Viswanathan N, Chu C. An effective floor- plan-guided placement algorithm for large-scale mixed- size designs[J]. ACM Transactions on Design Auto- mation of Electronic Systems, 2014, 19(3) :1-25.
  • 3罗佐,杜世民,戚利侠,夏银水.基于快速模拟退火算法的可切割布图规划方法[J].微电子学与计算机,2012,29(9):109-112. 被引量：2
  • 4WuGM, WuSW, ChangYW, etal. B*-Trees: a new representation for non-slicing floorplans [C]// Proc of ACM/IEEE Design Automation Conference. LOS Angeles, California, USA. IEEE, 2000 : 458-463.
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二级参考文献13

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共引文献15

同被引文献8

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二级引证文献5

微电子学与计算机
2016年 第11期

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