摘要
随着超高频RFID标签的应用越来越广泛,在提高其性能上的需求也越来越迫切。对于无源标签,工作距离是一个非常重要的指标。要提高工作距离,就要降低标签的功耗。着重从降低功耗方面阐述了一款基于ISO18000-6TypeC协议的UHF RFID标签基带处理器的设计。简要介绍了设计的结构,详细阐述了各种低功耗设计技术,如动态控制时钟频率、寄存器复用、使用计数器和组合逻辑代替移位寄存器、异步计数器、门控时钟等的应用。结果证明,这些措施有效地降低了功耗,仿真结果为在工作电压为1V,时钟为2.5MHz时,功耗为4.8μW;目前实现了前三项措施的流片,测试结果表明工作电压为1V,时钟为2.5MHz时,功耗为8.03μW。
Considering that RFID application is becoming increasingly wider, it is urgent to improve the performance of RFID tag. For passive RFID tag, one of the important specifications is operating distance, which can be extended by reducing the power consumption of tag. The digital baseband design of UHF RFID tag based on ISO18000-6 Type C protocol was presented, and some low power design technologies were introduced. RFID application and ISO18000-6 Type C protocol were introduced, the architecture of the design was described. A series of low power design strategies were given, such as dynamic control of clock, reuse of registers, using counter and combinational logic instead of shift registers, asynchronous counter, clock-gating, etc. The simulation results indicate that the power of digital baseband processor are reduced effectively, which is about 4.8 μW under 2.5 MHz clock frequency with 1 V power supply. And the chip which implemented the first three strategies consumes 8.03 μW under 2.5 MHz clock frequency with 1 V power supply.
出处
《半导体技术》
CAS
CSCD
北大核心
2009年第5期502-505,518,共5页
Semiconductor Technology
基金
国家高技术研究发展计划(863计划)(2006AA04A109)
