摘要
近年来,FPGA(Field Programmable Gate Array)设计验证技术成了当前的研究热点,设计的可靠性影响着产品的可靠性,因此验证工作变得尤为重要。但是随着产品更新换代速度的加快,传统的验证方法的停滞不前使得验证面临着严峻的挑战,因此鉴于现在验证的瓶颈,提出一种高效的验证方法,即在DUT(Design Under Test)实现之前先进行功能模型的编写,经过验证后重用做参考模型,能有效解决传统验证所面临的问题,提高了验证效率和准确率。
Nowadays,the technology of the design and verification of FPGA has become the hotspost of todays＇ research.The reliability of the design infulence the reliability of the production.Therefore the study of verification become quite important.As the fast speed of the update of the production.The stagnant development of the traditional method of verification makes the verification face with the austere challenge.So be based with the present choke point,we put forward a high-efficiency methods for verification.That is write the function model before the implement of DUT（Design Under Test）.After the verifying to the function model,it can be reused as the reference model.This method can deal with the problem that the traditional verification was faced with.It also enhance the efficiency and the accuracy rate of the verification.
出处
《电子质量》
2016年第3期70-79,共10页
Electronics Quality
