摘要
介绍了循环冗余效验(CRC)的实现原理和实现方法,串行实现方法占用资源少、简单可行,但效率较低;并行实现方法可以同时完成多位CRC计算,但占用的硬件资源多。为了提高CRC计算效率并减少资源消耗,提出了一种并行CRC编码方法并以CRC-16为例,采用Altera公司的Arria V GX系列FPGA芯片5AGXFB3H4F35C4N实现了带CRC效验的异步串口通信(UART),调用仿真工具Active-HDL,仿真结果显示该种方法消耗的硬件资源较少,能在输入发生变化的下一个时钟完成CRC并行计算。
A new parallel cyclic redundant check（CRC）encoding method is proposed in this paper after the introduction of CRC implementation theory and realization method.Serial implementation method takes less resources,but the efficiency is low;While parallel implementation method can complete several bits of CRC calculation at the same time,but takes too much hardware resources.In order to improve the CRC calculation efficiency and reduce resource consumption,this paper proposes a parallel CRC encoding method and then take CRC-16 for example,use the Arria V GX series FPGA chip 5AGXFB3H4F35C4 N produced by Altera corporation to realize the universal asynchronous receiver/transmitter（UART）communication containing the proposed new CRC encoding method.Finally,call the simulation tool Active-HDL,the result shows that this method consumes less hardware resources and has the ability to complete the parallel CRC computing at the next clock after the input changed.
出处
《电子测量技术》
2016年第2期147-150,共4页
Electronic Measurement Technology
