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倒装焊电子封装底充胶分层研究 被引量:3

Research of underfill delamination of flip chip
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摘要 使用裂缝尖端附近小矩形路径J积分方法计算电子封装分层传播的能量释放率,并在热循环加载下使用高频超声显微镜技术测定了B型和D型两种倒装焊封装在焊点有无断裂时芯片/底充胶界面的分层裂缝扩展速率。由有限元模拟给出的能量释放率和实验测得的裂缝扩展速率得到可作为倒装焊封装可靠性设计依据的Paris半经验方程。 The strain energy release rates G we re calculated by employing the J -int egral in a small rectangular path near the crac k tip in the related finite element simulations.And under thermal cycling loading,the crack p ropagation rates of two types of test chip(type B and D)were determined by using C -SAM inspectio n.The Paris half -empirical equatio n,which can be used as a design base of flip chip package reliability,is determined from the energy release rates simulated and the crack propagation rates measured.
出处 《功能材料与器件学报》 CAS CSCD 2002年第2期144-148,共5页 Journal of Functional Materials and Devices
基金 国家自然科学基金重点项目(批准号:19834070) 上海市科技发展基金项目(No.99ZD14055)
关键词 电子封装 倒装焊 底充胶分层 有限元模拟 能量释放率 flip -chip interfacial delamination finite element simulation str ain energy release rate
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参考文献11

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同被引文献24

  • 1GOTUACO M,LEE P W.The case for CVD low-k technology[J].Semicond Fabtech J,2001,15(6):179-183.
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  • 6GUPTA V,O’CONNER S,PILCH C.Chip package interaction induced ILD integrity issues in fine pitch flip chip packages[C]∥Proceedings of IEEE CPMT Electronics Packaging Technology Conference.Singapore,2014:482-486.
  • 7TISMER S,BRAND S,KLENGEL S,et al.Acoustic imaging of bump defects in flip-chip devices using split spectrum analysis[C]∥Proceedings of International IEEE Ultrasonics Symposium(IUS).Prague,Czech Republic,2013:950-953.
  • 8JEDEC Solid State Technology Association.IPC J-STD-030 guideline for selection and application of underfill material for flip chip and other micropackages[S].USA:Electronic Industries Alliance,2005:6-9.
  • 9JEDEC Solid State Technology Association.IPC/JEDEC J-STD-035 acoustic microscopy for nonhermetic encapsulated electronic components[S].USA:Electronic Industries Alliance,2010:1-8.
  • 10郭丹,杨道国.湿热载荷对含底充胶的FCOB器件界面分层影响[J].电子元件与材料,2008,27(4):65-68. 被引量:2

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