摘要
本文阐明了基于冗余抑制技术的低功耗电路的设计原理 ,分析了在组合电路中冗余行为的各种抑制结构及工作机理 .作为设计实例 ,本文提出了基于冗余抑制技术的低功耗比较器设计 .
The low power design principle based on redundancy restraining technique is explained in this paper.Various constructions for restraining redundancy in combinational circuits and their working mechanism are analyzed.Furthermore,a low power magnitude comparator design based on this technique is proposed.PSPICE simulation and energy analysis proves that saving energy dissipation can be effectively achieved by using this design technique.
出处
《电子学报》
EI
CAS
CSCD
北大核心
2002年第5期672-675,共4页
Acta Electronica Sinica
基金
国家自然科学基金 (No .697730 34)
宁波市青年基金 (No .0 1J2 0 30 0 2 7)
关键词
冗余抑制技术
低功耗
组合电路设计
CMOS
low power
redundancy restraining
magnitude comparator
