摘要
分析了边界扫描测试技术的工作机制对测试主控系统的功能需求 ,提出了一种基于微机PCI总线的低成本边界扫描测试主控系统的硬件设计方案 .该系统以PC机为平台 ,以用CPLD器件实现的JTAG主控器生成满足IEEE114 9.1协议的边界扫描测试信号 ,并用普通的SRAM实现存储器共享 .仿真表明 ,该系统产生的测试信号完全满足IEEE114 9.1协议的时序要求 ,可用于IC或PCB的边界扫描测试 ,以及进行边界扫描测试的研究和实验 .
The mechanism of boundary scan test and the functional requirement of boundary scan tester are analyzed, and a PCI based boundary scan testing system is presented. In the system, PC works as a platform, the JTAG controller used to generate the boundary scan testing signals is realized by using CPLD chip, and normal SRAM chips is used as the shared memory. So the system is characterized by the whole function, convenience in using and low price. It can be used in the boundary scan testing of IC and PCB, as well as in the research and experiment of the technology.
出处
《华中科技大学学报（自然科学版）》
EI
CAS
CSCD
北大核心
2002年第5期22-24,共3页
Journal of Huazhong University of Science and Technology(Natural Science Edition)
基金
航天创新基金资助项目
