摘要
时序设计是数字系统性能的关键 ,在高层设计方法中对时序的控制进一步抽象 ,我们在介绍电路时钟和时序的基础上分析了 RTL 电路的时序模型 ,该模型讨论了 RTL 电路的时延路径、建立保持时间以及系统正常工作的条件 ,并据此提出了相应的设计策略 。
Timing design is the key factor to of the performance of the digital system and it is more abstract in the high level design method. We introduce the clock and timing method of the digital current and then analyzing the timing model of the RT level circuit. This model discuss the timing path, setup hold time of the RTL circuit and the working conditions of the system, base on which we propose the corresponding policy which is effective in the practical design.
出处
《小型微型计算机系统》
CSCD
北大核心
2001年第9期1150-1152,共3页
Journal of Chinese Computer Systems
基金
"九五"国防预研课题"军用 MPU
MCU技术"( 8.1.3.5 )资助
