摘要
为解决控制流综合用时过多而造成的电路设计周期较长的问题 ,从分析控制流综合的基本步骤和现存问题入手 ,着眼于控制流综合所接收的有限状态机的特殊性 ,讨论了省略状态化简的可行性 ;并且给出了在 EDA综合工具中省略状态化简的具体实施方案 .
To solve the problem that control flow synthesis takes so much time that circuit design cycle is prolonged, this article analyzes the basic steps and problem of control flow synthesis, focusing on the special circumstance of finite-state machine that is handled by control flow synthesis, and discusses the feasibility of omitting the step of state reduction to save time. This article also puts forward a concrete scheme to omit the step of state reduction in EDA synthesis tool.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2001年第8期679-683,共5页
Journal of Computer-Aided Design & Computer Graphics
基金
国家自然科学基金项目 (69973 0 0 )资助
关键词
控制流综合
有限状态机
状态化简
状态分配
数字系统
control flow synthesis, finite-state machine, state reduction, state assignment, data flow synthesis
