摘要
本文讨论在设计同步时序逻辑电路时,就构成的实际逻辑电路的复杂程度而论,可能的、不同的基本状态分配数,以及选择良好的状态分配的若干有效的规则。
This paper deals with the number of possible different state assignments considering the complexity of a physical logical circuit, and some effective rules for selecting good state assignments when designing a synchronous sequential logical circuit.
关键词
状态分配
逻辑电路
逻辑相邻
state assignment
logical circuit
logical adjacency
