摘要
通过研究调整线段和线间距对串扰的影响 ,提出了一种在布线时通过采取作线段摄动和压缩线间距的措施来减小串扰的优化算法 .计算机仿真结果表明 ,该算法能有效地减少芯片中的串扰 .此外 。
One of major concerns in physical design of deep submicron VLSI circuits is to minimize the influence of crosstalk which will affect the chip's performance significantly if the designer does not pay attention to it in the phase of detailed routing. By studying how crosstalk is varying when adjusting wire's segment and space between neighboring wires, an optimization algorithm aimed at minimizing crosstalks by wire perturbation and space compression is developed in this paper. Computer simulation results show that the algorithm is effective in significantly decreasing chip's crosstalk. It is expected that the algorithm is applicable in the case of irregular routing areas.
出处
《计算机辅助设计与图形学学报》
EI
CSCD
北大核心
2001年第4期289-293,共5页
Journal of Computer-Aided Design & Computer Graphics
基金
中国博士后基金和
川省科技厅应用基础研究专项经费资助
关键词
超大规模集成电路
物理设计
串扰最小化
优化算法
VLSI
计算机仿真
VLSI circuit's physical design, detail routing, crosstalk minimization, wire perturbation, wire space compression
