摘要
以DDR高速总线为例,通过对DDR源同步时序的分析,以此提供一个高速PCB设计中高速总线时序完整的分析方法,从而使设计中的高速总线频率达到真正高速度和大的时序裕量。在此创新地在时序分析过程打破纯粹的理论公式推导,结合仿真分析软件,采用理论计算和仿真图形相结合的方法,使时序分析变得更加简化和直观。这种分析方法在其他高速总线分析中也得到广泛应用,并在实践中得到有效验证。
Taking high-speed DDR bus as an example,a complete time-sequence analysis method about high-speed bus in high-speed PCB design is proposed according to the DDR source synchronization time-sequence analysis to enable the frequency of high-speed bus in design to achieve really high-speed and large time-sequence margin. The innovation of this paper lies in the time-sequence analysis process,which breaks the purely theoretical formula derivation and makes time-sequence analysis be-come more simple and intuitive by combining with simulation analysis software and adopting the method of combining theoretical calculation with simulation graphics. This analysis method has been widely used and well proven in practice in other high-speed bus analyses.
出处
《现代电子技术》
2014年第8期75-78,共4页
Modern Electronics Technique
