3[1]Thomas M Niermann,Wu-Tung Cheng,Janak H Patel.PROOFS:A Fast Memory-Efficient Sequential Circuit Fault Simulator[J].IEEE Trans.on Computer-Aided Design,1992,11(2).198 ～ 207.
4[2]N Gouders,R Kaibel.PARIS:A Parallel Pattern Fault Simulator for Synchronous Sequential Circuit[J].IEEE Int Conf on CAD,Nov,1991,542 ～ 545.
5[3]P R Menon,Y Levendel,M Abramovici.SCRIPF:A critical path tracing algorithm for synchronous sequential circuits[J].IEEE Trans on Computer-Aided Design,CAD-10(6),1991,6:738 ～ 747.
7[5]M Abramovici,P R Menon,D T Mill.Critical Path Tracing:An Alternative to Fault Simulation[J].IEEE Design and Test of Computers,Feb.1994,83 ～ 93.
8[6]J A Waicukauski,E B Eichelberger,D O Fortenza,E Lindbloom,Thomas McCarthy.Fault Simulation for Structured VLSI[J].VLSI Syst.Design,1985,12:p20 ～ 32.
9[7]K Antreich,M Sohulz.Accelerated Fault Simulation and Fault Grading in Combinational Circuits[J].IEEE Trans.on Computer-Aided Design,vol.CAD-6,1987,9:704-712.
10[1]Thomas M, Niermann, Wu-Tung Cheng, Janak H. Patel, PROOFS: A fast memiry-efficient sequential circuit fault simulator. IEEE Trans. on Computer-Aided Design, 1992,11 (2): 198～207.
