摘要
针对常规测速方法存在的精度差和测量滞后严重的问题,在通用的M/T法的基础之上,提出了一种基于可编程逻辑器件(FPGA)的速度动态估算方法。利用FPGA的高效的数字信号处理能力,将增量式光电编码器反馈信号进行了四倍频细分,通过Verilog HDL语言编程设计了时间阀门、计数等相关模块。利用小数估计不完整脉冲的思想,采用动态的速度估算方法估算了速度值,通过一阶低通滤波器滤波得到了结果。研究结果表明,该方法无论应用于低速还是高速情况下,测量的精度都有所提高,而且测量的滞后减小可以控制在一定范围内。
Aiming at the problems of the poor accuracy and the serious lag in the conventional methods of measuring velocity, a new dynamic estimated method for velocity estimating based on the common M/T method was proposed. This method was designed with field programmable gate array （FPGA） for its powerful digital processing ability and the feedback signals of the incremental photoelectric encoder were quadrup- led. The time constant, counting and other related modules were designed by using the verilog HDL programming language： The idea that the incomplete pulses were estimated by using decimals was adopted. The velocity which was calculated by using the dynamic estimated methods should pass through a low-pass first order filter. The results indicate that, no matter whether velocity is low or high, this method improves the accuracy and reduces hysteresis, and the hysteresis can be controlled in a certain range.
出处
《机电工程》
CAS
2013年第11期1420-1424,共5页
Journal of Mechanical & Electrical Engineering
基金
国家自然科学基金资助项目(51305404)
国家科技支撑计划资助项目(2013BAF05B01)
浙江理工大学重点实验室优秀青年人才培养基金资助项目(ZSTUMD2012B004)
关键词
M
T法
现场可编程门阵列
速度估算
M/T method
field-progrannnble gate array（FPGA）
estimation of velocity
