摘要
为提高射频功放的线性和效率,提出了一种基于多比特带通△∑调制器(BPDSM)的射频数字功放结构并给出了BPDSM的设计方法。针对调制器CRFB实现结构中关键路径过长的问题,利用重定时、流水线和超前计算等技术对实现结构进行了改进,将BPDSM的实现速率提高至200 MHz。提出了多电平开关功放的电路结构,将多个具有独立电源的开关功放单元进行串联,实现了对BPDSM输出多比特脉冲信号的高效开关放大。最后,利用FPGA器件及分立元件实现了频率为30 MHz的数字功放,输出功率为10 W时效率达到60%。
To achieve better efficiency and linearity, RF digital power amplifier architecture utilizing multi-bit bandpass delta sigma modulator （BPDSM） is proposed. In this paper, design methodology of multi-bit BPDSM is presented. In order to short the critical path, classical CRFB architecture is modified by using retiming, pipeline and pre-calculation, the max frequency of new ar chitecture can reach 200 MHz. In addition, architecture of multi-level switch mode power amplifier is designed, it combines muhi ple switch power amplifier cells with its own power supply in serials, realizing efficient amplification of multi-bit pulse signals. Fi nally, based on FPGA and lump components, a digital power amplifier with output frequency of 30 MHz and power efficiency of 60.6% at lOW output is implemented.
出处
《电子技术应用》
北大核心
2013年第8期102-104,108,共4页
Application of Electronic Technique
