摘要
介绍了一种基于 ISA总线的高速数据采集系统构成及各部分功能。对提高高速数据采集系统的采样率和存储器带宽这两大技术难题提出了补救措施。采用交替采样合成方式实现了系统最高采样率的倍增 ;采用多体存储结构提高了系统存储带宽 ;利用复杂可编程控制逻辑 (CPL D)设计了系统控制逻辑、地址产生器、数据地址总线隔离器。文中最后给出了实际测试结果。
The construction of a high speed data acquisition system based on ISA bus and the function of each part of the system it are introduced. The compensating measure is put forward to solve the two technological problems of sampling and memory bandwidth enhancement of high speed data acquisition systems. The double enhancement of the high sampling rate of the system is realized by the alternating sampling synthesizing method. The system memory bandwidth is enhanced through the multi body storage architecture. The system control logic, the address generator and the data bus separator are designed with a complex program logic device (CPLD). Finally, experimental results are given.
出处
《数据采集与处理》
EI
CSCD
2000年第2期245-247,共3页
Journal of Data Acquisition and Processing
关键词
高速数据采集系统
ISA总线
设计
单元电路
memory
data acquisition
data transfer
sampling rate
complex program logic device(CPLD)
