摘要
针对专用集成电路(ASIC)设计中功能验证的效率和完备性问题,以验证方法学手册(VMM)为基础搭建了串行高级技术附件(SATA)控制器分层式验证平台.验证组件的实现大量重用验证知识产权核(VIP),在采用随机激励的基础上以覆盖率统计驱动验证的过程,根据SATA控制器的功能设计记分牌进行结果的自动化比对.实验结果表明,这些方法提高了功能验证的效率,保证了验证的完备性,最终功能覆盖率达到98.25%.
According to the efficiency and completeness in the function verification of the application specific inte- grated circuit（ASIC）design, we constructed the serial advanced technology attachment （SATA）controller~ s layered verification platform in the direction of verification methodology manual （VMM） verification methodology. The verifi- cation components were realized by reusing many verification intellectual property （VIP）. The course of verification was driven by function coverage statistics based on random stimulus, and the results were checked automatically by the scoreboard according to the SATA controller. The experimental result showed that these methods improved the functional verification efficiency, ensured the completeness, and the final function coverage reached 98.25%.
出处
《武汉大学学报（理学版）》
CAS
CSCD
北大核心
2013年第3期223-227,共5页
Journal of Wuhan University:Natural Science Edition
基金
中国海思半导体有限公司视频监控项目(HI35XX)
关键词
验证方法学手册
验证平台
串行高级技术附件
验证知识产权核
verification methodology manual
verification platform
serial advanced technology attachment
verifi-cation intellectual property
