摘要
本文在分析了单片JPEG2000压缩标准的专用编解码芯片ADV212的硬件结构和工作原理的基础上,实现了基于ADV212的图像压缩系统的硬件设计和FPGA逻辑设计。其中,该系统的数据输入接口采用LVDS,数据输出接口采用USB,FPGA主要实现对压缩芯片ADV212寄存器的配置,整个系统的数据流控制以及系统时序逻辑适配。实验结果表明,该系统满足系统对图像压缩实时性的要求,同时,重构后的图像与原始图像进行相比,具有较高的峰值信噪比(PSNR)。
Based on analyzing the hardware structure and running principle of the ADV212 single-chip JPEG 2000 codec, this paper implement the design of image compressing system including hardware design and FPGA logic design. For a typical encode application, it receives the bus LVDS serial data stream, and sends the compressed image data through the bus USB. We configure the ADV212 registers and control the timing with FPGA. The results of this experiment shows the image compressing system satisfy the need of real--time, at the same time, comparing with the original image, the compressing image have a high PSNR.
出处
《科技创新导报》
2013年第11期152-154,共3页
Science and Technology Innovation Herald
