摘要
为了提高Huffman解码的效率和实时性,采用并行处理技术和改进的Huffman并行解码算法,设计基于现场可编程门阵列FPGA的Huffman并行解码器。在不考虑Huffman编码长度的情况下,解码器通过插入流水线结构的方法将Huffman码流的码流头和信息码流分开,同时进行解码。硬件仿真结果表明,在一个时钟节拍内解码器处理的数据位数与解码效率成正比,位数越多,实时性越好。
In order to improve the Huffman! decoding efficiency and real time, it designs and implements Huffman parallel decoder based on FPGA, through the use of parallel processing technology and huff man parallel decoding algorithm. Through the pipeline structure methods, the decoder is inserted l-luffman stream head stream and information stream separately which they are decoding at the same time without considering the Huffman coding length of the case. The simulation results show that the number of data bits the decoder processing in a clock is proportional to decoding efficiency, meanwhile the more digits of the bits, the better real time. With Huffman serial decoder decoding methods, Huffman parallel decoder improved Huffman serial decoding technology of low efficiency and poor real time.
出处
《微型机与应用》
2013年第11期84-86,共3页
Microcomputer & Its Applications
基金
陕西省自然科学基金(2011JM8038)
