摘要压缩方法对于频道带宽或者存储容量有限的系统而言是非常重要的。我们可以完成一种实时的并行Huffman解码器的硬件设计,它在FPGA上的实现需要用到50,000个门(FLEX10K20 from Altera)。运用并行技术,一个码字将在一个时钟周期里面解完。为了节省存储器的开销,我们给出了一种优化的查找表。这篇论文主要是介绍了一种可行的实时解码器的设计。
1[1]M.Kovac,N.Ranganathan."JAGUAR:A Fully Pipelined VLSI Architecture for JPEG Image Compression Standard",Proceeding of the IEEE,83,IIO.2,Feb 1995
2[2]Kesab K.Parhi.1992."High-Speed VLSI Architecture for Huffman and Viterbi Decoders."IEEE TRANSACTION ON CIRCUITS AND SYSTEMS-Ⅱ:ANALOG AND DIGITAL SIGNAL PROCESSING.39,no.6 (JUNE):385-391.
3[3]Peter Pirsch,Nicolas Demassieux.and Winfried Gehrke.1995."VLSI Architectures for Video Compression-A Survey." Proceeding of IEEE,83,no.2(February):220～244.
