摘要
针对智能变电站中对合并单元时间性能指标上较高的技术要求,文中通过对由插值算法进行同步的合并单元实现原理的具体分析,充分利用PowerPC的计算能力和现场可编程门阵列(FPGA)的并行处理能力,将整个系统分成多个模块,并通过模块间的相互配合,提出一种具体的合并单元关键环节的设计方案。在该方案中,通过对连续有效秒脉冲间隔的统计和记录,来实现高精度的守时模块,并利用灵活设置的定时器中断周期,来对合并单元的重采样时刻进行动态调整,使之与外部对时信号同步。同时通过对输出延时的分解及FPGA的缓存功能,精确实现了SV9-2报文的等间隔输出。
In view of the rather high requirement of time performance for the merging unit in the smart substation,through the concrete analysis on the implementation principle of the merging unit using the interpolation algorithm,and by fully utilizing the computing performance of PowerPC together with the parallel processing capabilities of FPGA,the whole system is divided into several cooperated models and a design solution of key links for merging unit is presented.In this solution,a high precision time-keeping model is realized by the statistics and records for the continuous and effective pulse per second（PPS） interval.To realize synchronization with the external time signal,a dynamic adjustment method for time resampling is presented through the flexible setting for interrupted cycle of timer.At the same time,an equal interval output of SV9-2 datagram is accurately realized through the division of output delay and caching feature of FPGA.
出处
《电力系统自动化》
EI
CSCD
北大核心
2013年第11期93-98,共6页
Automation of Electric Power Systems
关键词
智能变电站
合并单元
插值算法
同步
守时
输出延时
smart substation
merging unit
interpolation algorithm
synchronization
time-keeping
output delay
