摘要
为了实现不同速率数据链路通信的相互转换,提出了一种利用现场可编程门序列(FPGA)设计并实现可对同步动态随机存储器(SDRAM)进行数据缓存并高速读写的控制器.该控制器采取状态机和令牌环机制,通过对SDRAM操作,实现了双向4路的跨时钟域的匹配.该控制器适用于任意长度的以太网帧和其他类型的数据相互转换.
In order to achieve communication based on asynchronous clock, this essay comes up with asynehronous dynamic random access memory （SDRAM） controller,which can store data in and reload from SDRAM by read/write operation with high speed, for data cache. According to operating the SDRAM, this controller allows bidirectional asynchronous data to rematch in SDRAM by using state machine and token ring mechanism. It is also suitable for communication between other data and Ethernet frame with random length.
出处
《厦门大学学报（自然科学版）》
CAS
CSCD
北大核心
2013年第3期360-365,共6页
Journal of Xiamen University：Natural Science
基金
福建省自然科学基金项目(2012H0038)
