摘要
针对测控系统中单一FPGA的IO口不足,无法满足高采样率,上百路通道并行采集情况,提出了基于异步FIFO(先入先出队列)存储的多片FPGA大规模并行信号采集模块。该模块通过将多片FPGA采集数字信号的高低状态存储在内建FIFO里,然后将数据编帧存储在FLASH中,通过USB接口与上位机连接。仿真表明:该模块可采集400路数学信号,结构灵活、控制简单、可靠性较高,数据采集通道可根据需要进行扩展。
Because of the monitor system＇s IO ports on single FPGA was insufficient, which could not meet the requirement of a high sampling rate of hundreds monitoring signals, this paper introduced a multi-channel paral- lel digital signal collecting module based on asynchronous FIFO of multiple FPGA chips. It collected low or high states of the digital signals and memories in the FIFO; then, it was made into lame structure and memories in the FLASH~ finally, it connected with the host computer via USB interface. The simulation results indicated that the collecting module of 400 hundred digital signals was easy to be modified, controlled, and was high relia- bility. Its sampling signal routes could be expanded in the light of the users need.
出处
《探测与控制学报》
CSCD
北大核心
2013年第2期55-58,共4页
Journal of Detection & Control
基金
教育部科学技术研究重点项目资助(211027)
山西省科技厅基础条件平台建设项目资助(2010091013)
