摘要
为了提高数据处理效率,BCH编译码电路都采用并行结构,但是并行结构大幅度增大电路的面积消耗及逻辑延迟。对并行钱氏搜索中占主要资源的单变量乘法器进行优化。仿真综合结构表明,BCH码(16 459,16 384,5)在此简化乘法器的基础上,其并行结构电路在面积资源的优化率可达81.9%,关键路径延迟的优化率可达66.4%。
In order to improve the data processing efficiency, the BCH coder and decoder circuit both adopt parallel structure. The single variable finite field multipliers which occupy the main resources of parallel Chien search circuit is optimized in this paper. Synthetic simulation shows that, BCH code（16 459, 16 384, 5） on the basis of the simplified multiplier, parallel structure circuit resources optimization rate can be 81.9% in the area and the critical path delay optimization rate can be 66.4%.
出处
《电视技术》
北大核心
2013年第11期1-3,11,共4页
Video Engineering
