摘要
DVB-S2是新一代数字卫星广播标准,标准采用了新的调制与编码技术,在一定的复杂程度下取得最大的信道容量与较好的系统可扩展性。其中编码方式采用了由BCH与LDPC级联的前向纠错系统,使系统性能接近香农限,但长二进制BCH码,也极大地增加了译码器硬件实现难度。针对标准中BCH码的特殊性,通过对长BCH码优化方法的研究与讨论,提出实现该译码器简单有效的FPGA硬件结构,在满足速度要求的前提下尽量减小面积。
DVB - S2 is the new standard of Digital Satellite Broadcasting. It adopts new technology of modulation and encoding, which help to achieve the largest channel capacity and good extension of system with certain complexity. The standard adopts Forward Error Correcting （FEC） encoding based on LDPC concatenated with BCH codes, which provides the performance near Shannon limit. But the long BCH codes bring big challenges for hardware implementation of the decoder. This paper discusses on several methods of optimization for long BCH decoder,and provides an effective architecture for FPGA according to the standard＇s BCH codes which meets the request of speed and minimizes chip＇s area.
出处
《现代电子技术》
2007年第21期25-27,33,共4页
Modern Electronics Technique
