摘要
根据电力设备通信的同步性要求,提出了一种数字锁相环的设计方案。采用VHDL设计语言,运用Modelsim仿真软件进行设计,根据波形图深入分析了数字锁相环的工作过程以及变模K值对结果的影响,并在CPLD上实现数字锁相环的实际应用,得到了较为理想的设计指标。
Based on the requirements of power equipment communication, this paper raises an effective solution of digital phase locked loop based on VHDL language, and carries out the simulation test with Modelsim software. The working process of the digital PLL is analyzed according to the wave figures. The influence of the variable modulus K on the result is discussed, the application on CPLD is realized, and the ideal design indexes are got.
出处
《机械工程与自动化》
2013年第2期57-59,共3页
Mechanical Engineering & Automation
