4Shivakumar P, Kistler M, Keckler S W, et al. Modeling the effect of technology trends on the soft error rate of combinational logic[C] // Proceedings of International Conference on Dependable Systems and Networks, Washington, D. C., 2002: 389-398.
4Majzik I, Hohl W, Pataricza A, et al. Multiproeessor checking using watchdog processors [J]. International Journal of Computer Systems Science and Engineering, 1996, 11(5): 301-310
5Alkhalifa Z, Nair V S S, Krishnamurthy N, et al. Design and evaluation of system-level checks for on-line control flow error detection [J]. IEEE Trans on Parallel and Distributed Systems, 1999, 10(6): 627-641
6Goloubeva O, Rebaudengo M, Sonza R M, et al. Soft-error detection using control flow assertions [C]//Proc of IEEE Int Symp on Defect and Fault Tolerance in VLSI Systems. Los Alamitos, CA.. IEEE Computer Society, 2003:581-588
7Oh N, Shirvani P, McCluskey E J. Control flow checking by software signatures [J]. IEEE Trans on Reliability, 2002, 51(2): 111-122
8Venkatasubramanian R, Hayes J P, Murray B T. Low-cost on-line fault detection using control flow assertions [C]// Proc of IEEE On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2003:137-143
9Fazeli M, Farivar R, Miremadi S G. A software-based concurrent error detection technique for PowerPC processorbased embedded systems[C] //Proc of IEEE-Int Syrup on Defect and Fault Tolerance in VLSI Systems. Los Alamitos: IEEE Computer Society, 2005:266-274
10Czech E W, Siewiorek D. Effects of transient gate-level faults on program behavior [C]//Proc of IEEE Int Fault-Tolerant Computing Symposium. Los Alamitos, CA: IEEE Computer Society, 1990:236-243
