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功率Trench MOS器件工业化技术的新进展 被引量:1

Recent Progress of Power Trench MOS Industrialization Technology
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摘要 简要地回顾和探讨了垂直型功率Trench金属氧化层半导体场效晶体管(MOSFET)器件(即Trench MOS)的技术发展及其当前工业化生产水平。重点讨论了适用于工业界大规模生产的,能同时降低正向导通损耗和瞬态开关损耗的器件结构和制造工艺,并举例给出了目前工业界最先进30 V Trench MOS产品综合技术指标(FOM)的比较。最后,讨论了沟槽技术在基于SiC材料的功率MOSFET器件生产中的应用。 The technology progressive development and the industrial production status of trench-gated vertical power metal-oxide-semiconductor field-effect transistor(MOSFET) are briefly reviewed and discussed.The emphases are given to the techniques for minimizing both condition loss and switching loss with good industrialization yield for mass production.The latest figure of merit (FOM) of 30 V Trench MOS products is presented as example for technology comparison.Finally,the utilization of trench technology in the production of SiC based power MOSFET is discussed.
出处 《电力电子技术》 CSCD 北大核心 2012年第12期18-21,共4页 Power Electronics
关键词 金属氧化层半导体场效晶体管 工业化技术 综合技术指标 metal-oxide-semiconductor field-effect transistor industrialization technology figure of merit
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  • 1Y Tarui,Y Hayashi,T Sekigawa.Diffusion Self-aligned Enhance-Depletion MOS-IC[J].Journal of the Japan So- ciety of Applied Physics, 1971,40 : 193-198.
  • 2F E Holmes,C A T Salama.VMOS-A New MOS In- tegrated Circuit Technology [J]. Solid State Electronics, 1974,17.
  • 3C A T Salama.A New Short Channel MOSFET Structure (UMOST)[J].Solid State Electronics, 1977,20.
  • 4D Ueda, H Takagi, G Kano.A New Vertical Power MOS- FET Structure With Extremely Reduced On-resistance[J]. IEEE Trans. Electron Devices, 1985,32( 1 ).
  • 5R A Blanchard.Method for Making Planar Vertical Chan- nel DMOS Structures[P].US Patent 4767722,1988.
  • 6C Kocon,J Zeng.High Density MOS-Gated Power Device and Process for Forming Same[P].US Patent 6188105.
  • 7J Zeng, et al.An Ultra Dense Trench-gated Power MOS- FET Technology Using A Self-aligned Process[A].ISPSD[C]. 2001.
  • 8J Zeng, G Dolny, C Kocon, et al.Brush, Power MOS DeviceWith Buried Gate and Groove [P]. US Patent 6445035, 6638826.
  • 9R A Blanchard.Grooved DMOS Process with Varying Gate Dielectric Thickness[P].US Patent 4914058.
  • 10V A K Temple.Semiconductor Devices Exhibiting Mini- mum On-resistance[P].US Patent 4941026.

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