摘要
研制了一种应用漂洗发射极晶体管和U型槽隔离技术的改进型肖特基晶体管逻辑电路(MSTL),它不仅具有标准STL高速度和ISL工艺简化的优点,与采用多晶硅发射极晶体管和氧化隔离技术的MSTL比较,进一步简化了工艺,且能在微功耗下工作.实验表明,采用4μm的设计规则,在50μA的工作电流下,传输延迟时间为3.2ns,速度功耗乘积为0.24pJ,集成度为190门/mm^2.
Using washed emitter transistor and the U-groove isolation technique, a modified Schottky transistor logic circuit(MSTL) was fabricated. It has the advantages of both high speed as the standard STL and the simplified process as ISL, but also more simplified process and lower power consumption as compared with the MSTL, which was fabricated by using polysilicon emitter transistor and oxide isolation technique. Experiments show that 3.2ns propagation delay time, 0.24pJ speed-consumption product and 190 gatas/mm2 packing density are obtained at 50μA operating current while the 4μm design rule is used.
出处
《固体电子学研究与进展》
CAS
CSCD
北大核心
1990年第1期34-38,共5页
Research & Progress of SSE
