摘要
根据雷达视频数据量大、目标信息较为重要的特点,设计并实现了一种基于FPGA的高分辨率雷达视频压缩方案。该方案针对压缩过程中算法较为复杂,且有大量浮点运算、乘法处理等高计算复杂度的问题,对DCT、量化、编码等核心处理模块分别进行了优化设计。在一片StratixⅣGX EP4SGX230KF40C4芯片上进行了验证,结果表明,该设计方案资源占用率低,压缩后图像质量较好,对于1600x1200分辨率的视频处理速度可达50帧/秒以上,满足高分辨率雷达视频实时压缩的要求。
According to the characteristics of radar video image that the data are large and the information of the aim target is small and important, a high resolution radar video image compression scheme is proposed and implemented on FPGA. The key modules as DCT, quantification, and encoder are designed respectively. The scheme is accom- plished in a Stratix IV GX EP4SGX230KF40C4 chip. The experimental results show that the rate of resources utilization is low and the image quality after compressed is good with the processing speed is higher than 50 frames per second for 1600 × 1200 resolution video image, it meets the requirements of high resolution radar video real-time compression.
出处
《自动化技术与应用》
2012年第6期38-41,51,共5页
Techniques of Automation and Applications
基金
中国博士后科学基金(编号2011M500940)
