摘要
硬件描述与验证语言System Verilog可以克服传统仿真验证方法的缺陷,使验证平台的搭建更加灵活,可重用性更强。开放验证方法学(Open Verification Methodology,OVM)是一个在验证环境中使用System Verilog对数字硬件进行功能验证的框架。OVM的组件由System Verilog的类组成,并按照良好的结构化和层次化原则,构成一个高质量、高效率、可重用的验证环境。论文介绍了OVM验证方法学的基本概念和组件,并且利用OVM验证方法学搭建了32位微处理器的验证平台。
SystemVerilog, a hardware description and verification language, can overcome the defects of traditional verification methods in simulation, and makes building testbench more flexible and reusable. OVM （Open Verification Methodology） is a framework for functional verification of digital hardware adopting SystemVerilog in simulation environment. OVM components are written as SystemVerilog classes to structure a high-quality, efficient and reusable verification environment in a well structured and layered way. This paper introduces the basic concepts and components of OVM, and builds a testbench of 32-bit microprocessor by OVM.
出处
《微计算机信息》
2012年第6期119-122,48,共5页
Control & Automation
