摘要
分析由辐射造成的单粒子翻转(SEU)软错误,在通用布局布线工具的基础上,提出一种基于SRAM结构的现场可编程门阵列(FPGA)抗辐射布局算法。该算法通过优化电路单元在FPGA中的布局位置,减少布线资源开路敏感错误、短路敏感错误以及SEU敏感点的数目。测试结果表明,该算法能减少SEU软错误,提高FPGA的抗辐射性能,并且无需增加额外的设计成本和硬件开销。
This paper proposes a radioresistance placement algorithm for Field Programmable Gate Array（FPGA） based on Static Random Access Memory（SRAM） on the base of academic Versatile Placement and Routing（VPR） tool.To achieve the goal of mitigating the number of the Single Event Upset（SEU） sensitive points,the cause of the soft error is analyzed and the positions of the programmable blocks are optimized by placement algorithm.The algorithm tests in a fault injection system which simulates the high radiation environment.Experimental results show that the algorithm can effectively reduce the SEU effects of SRAM-based FPGA in high radiation environment,improving the fault tolerance ability of the circuits implemented in the FPGA,and it does not need to add the extra design and hardware cost.
出处
《计算机工程》
CAS
CSCD
2012年第5期236-239,共4页
Computer Engineering
基金
"核高基"重大专项(2009ZX01034-002-004-003)
专用集成电路与系统国家重点实验室自主课题基金资助项目(09XT004)
关键词
现场可编程门阵列
抗辐射
布局算法
计算机辅助设计
单粒子翻转
软错误
Field Programmable Gate Array（FPGA）
radioresistance
placement algorithm
Computer Aided Design（CAD）
Single Event Upset（SEU）
soft error
