摘要
现有的大多数市售误码仪无法完成对实际工作中大量存在的特殊信道的误码测试,文中实现了一种基于FPGA的多接口码型、多传输速率的误码测试仪的设计。先从误码测试仪的基本原理框图入手,介绍它的各个功能子模块的作用,并侧重分析了误码测试仪的一些关键模块的工作原理及具体实现方法。在此基础上还给出了一种新的实现误码率统计的运算方法,使得系统用较少的逻辑资源实现了对误码测试结果的计算。误码仪选用了单片机和FPGA作为核心器件,提高它的升级和可移植能力。
Most of the existing commercial bit error rate tester（BERT） can not be completed on the actual work in the special channel for bit error test.BERT is presented based on FPGA chip,which is designed with multi-interface code patterns and multi-transmission rates,starting from the basic block graph of the error code instrument.Introduce the function of each module,then lay emphasis on discussion of the implementation method for the key module in the error code instrument.On this basis,also present a new statistical method to achieve error rate,avoiding insignificant division calculation and instead of less resource consumption to achieve bit error rate.BERT selected the single chip computer and the FPGA device for upgrading and improving its probability.
出处
《计算机技术与发展》
2012年第3期149-152,156,共5页
Computer Technology and Development
基金
南京邮电大学基金(NY207507)
