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用于MB-OFDM UWB系统的FFT/IFFT处理器的设计与实现 被引量：1

The design and implementation of FFT/IFFT processor for MB-OFDM UWB
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摘要 设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器。该处理器采用基24算法进行FFT运算,利用8路并入并出的流水线结构实现该算法,提高了处理器的数据吞吐率,降低了芯片功耗。提出了一种新颖的数据处理方式,在保证信噪比的情况下节约了逻辑资源。在乘法器的设计环节,针对UWB系统的具体特点,在结构上对乘法器进行了改进和优化,提高了乘法器的性能。最后,设计的FFT/IFFT处理器采用TSMC 0.18μm CMOS标准工艺库综合,芯片的内核面积为0.762mm2(不含测试电路)。在1.8V,25℃条件下,最大工作时钟317.199MHz,在UWB典型的工作频率下,内核功耗为33.5304mW。 A FFT/IFFT processor used in ultra-wideband （UWB） system is presented. The processor is based on the 24 FFT algorithm and can simultaneously deal with data of 8 data path, which can provide a higher throughput and lower power , dissipation. A new data structure is proposed to reduce the logic resources while the signal-noise-ratio （SNR） can satisfy the UWB system. The multipliers of the FFT/IFFT processor are improved and optimized in the structure to update the performance based on the characteristics of the UWB system. The FFT/IFFT processor is synthesized in TSMC 0.18μm technology with Synopsys＇s Design Complier, The core area is 0.762mm^2 （excluding the test module）. Under 1.8V supply and 25 ℃ condition, the maximum working frequency is 317.199MHz, the power dissipation is 33.5304mW in typical mode.
作者 管海亮 乔庐峰
机构地区 中国人民解放军理工大学通信工程学院
出处 《电路与系统学报》 CSCD 北大核心 2012年第1期120-125,共6页 Journal of Circuits and Systems
关键词 快速傅立叶变换 数据类型 常数乘法器 控制模块 FFT Data type constant multiplier control module
分类号 TN911.72 [电子电信—通信与信息系统]
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参考文献11

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二级参考文献21

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共引文献6

同被引文献15

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电路与系统学报
2012年 第1期

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